Charge-based compact model of gate-all-around floating gate nanowire with variable oxide thickness for flash memory cell

Due to high gate electrostatic control and introduction of punch and plug process technology, the gate-all-around (GAA) transistor is very promising in, and apparently has been utilized for, flash memory applications. However, GAA Floating Gate (GAA-FG) memory cell still requires high programming voltage that may be susceptible to cell-to-cell interference. Scaling down the tunnel oxide can reduce the Program/Erase (P/E) voltage but degrades the data retention capability. By using Technology-Computer-Aided-Design (TCAD) tools, the concept of tunnel barrier engineering using Variable Oxide Thickness (VARIOT) of low-k/high-k stack is utilized in compensating the trade-off between P/E operation and retention characteristics. Four high-k dielectrics (Si3N4, Al2O3, HfO2 and ZrO2) that are commonly used in semiconductor process technology are examined with SiO2 as its low-k dielectric. It is found that by using SiO2/Al2O3 as the tunnel layer, both the P/E and retention characteristics of GAA-FG can be compensated. About 30% improvement in memory window than conventional SiO2 is obtained and only 1% of charge-loss is predicted after 10 years of applying gate stress of -3.6V. Compact model of GAA-FG is initiated by developing a continuous explicit core model of GAA transistor (GAA Nanowire MOSFET (GAANWFET) and Juntionless Nanowire Transitor (JNT)). The validity of the theory and compact model is identified based on sophisticated numerical TCAD simulator for under 10% maximum error of surface potential. It is revealed that with the inclusion of partial-depletion conduction, the accuracy of the core model for GAANWFET is improved by more than 50% in the subthreshold region with doping-geometry ratio can be as high as about 0.86. As for JNT, despite the model being accurate for doping-geometry ratio upto 0.6, it is also independent of fitting parameters that may vary under different terminal biases or doping-geometry cases. The compact model of GAA-FG is completed by incorperating Charge Balance Model (CBM) into GAA transistor core model where good agreement is obtained with TCAD simulation and published experimental work. The CBM gives better accuracy than the conventional capacitive coupling approach under subthreshold region with approximately 10% error of floating gate potential. Therefore, the proposed compact model can be used to assist experimental work in extracting experimental data

Device modelling of archimedean spiral graphene nanoscroll field-effect-transistor

For the past decades, researchers indicate that persistent scaling of conventional silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) reaching its physical limit at 10nm, resulted in its performance degradation as the search continues for a low-power and high speed, density and reliability devices. The frailty due to the Short Channel Effects (SCE) has limited the device scaling. In addition, the emergence of Carbon Nanotube (CNT) in the past two decades has been a remarkable breakthrough in solving for transistor SCE; but there has also been a problem in controlling its band gap energy. Graphene Nanoscroll (GNS) is one of the carbon-based materials that inherit most likely similar electrical properties as CNT. But GNS possesses an advantage to modulate its properties by varying its carbon layer overlapping region owing to the open edge spiral, resulting in band gap variations. This study is to investigate the GNS carrier statistic against its geometry variation and its performance as a MOSFET. The carrier statistic such as the energy band gap, density of states, carrier density and intrinsic velocity were modeled and the results show strong relation to the overlapping region of GNS. The energy band gap exhibits an inverse relation to the overlapping region and metallic properties was restored when the overlap has reached certain limit. The carrier density also increases with the overlapping region as a sign of gap narrowing. Moreover, the intrinsic velocity increases with overlap region and remains constant as it reaches graphene Fermi velocity, signifying ballistic transport near Fermi point. The charge distribution in GNSFET was characterized based on the Landauer Buttiker’s formalism. The output current shows good agreement with the experimental results at constant conductance and GNS structural parameters. Furthermore, the GNSFET demonstrated comparable performance to the CNTFET within ballistic limit. The GNSFET was also benchmarked with the latest 22nm MOSFET technology, which indicates faster switching capability due to enhancement in Subthreshold Swing (SS) and Drain Induced Barrier Lowering (DIBL)